View TB62709FG_830750.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tb62709ng/fg toshiba bi ? cmos integrated circuit silicon monolithic tb62709ng,TB62709FG 7 ? segment drivers with built ? in decoders (common anode capability, maximum 4 ? digit control) the tb62709ng and TB62709FG are multifunctional, compact, 7 ? segment led display drivers. these ics can directly drive 7 ? segment displays and individual leds, and can control either a 4 ? digit display with decimal points, or 32 individual leds. these ics can also be used with common ? anode displays. their outputs are constant current, the ampere levels at which are set using an external resistor. a synchronous serial port connects the ic to the cpu. the different modes of control provided by this device including duty control register set, digit set, decode set and standby set, are all based on every 16 ? bit of serial data. this devices are a product for the pb free(sn-ag). features control circuit power supply voltage : v dd = 4.5 to 5.5 v digit output rating : 17 v / ? 400 ma decoder output rating : 17 v / 50 ma built ? in decoder : decodes the numerals 0 to 9, certain alphabetic characters, and of course blanks code. digit control function : can scan digit outputs dig ? 0 to dig ? 3 when connected to the common anode pins of a 7 ? segment display. maximum transmission frequency : f clk = 15 mhz decoder outputs (out ? a to out ? dp) output current can be set up to a 40ma maximum using an external resistor. constant current tolerance (ta = 25c, v dd = 5.0 v) : variation between bits = 7%, variation between devices (including variation between bits) = 15% at v ce 0.7 v package : 24 ? pin sdip (sdip24 ? p ? 300 ? 1.78) 24 ? pin ssop (ssop24 ? p ? 300 ? 1.00) tb62709ng TB62709FG weight sdip24-p-300-1.78 : 1.62 g (typ.) ssop24-p-300-1.00 : 0.32 g (typ.) web: www.marktechopto.com | email: info@marktechopto.com company headquarters 3 northway lane north latham, new york 12110 toll free: 800.984.5337 fax: 518.785.4725 california sales office: 950 south coast drive, suite 225 costa mesa, california 92626 toll free: 800.984.5337 fax: 714.850.9314
tb62709ng/fg 2005-10-06 2 pin assignment (top view) block diagram
tb62709ng/fg 2005-10-06 3 pin functions pin number pin name function 1 v dd 5 v power pin. 2 data in (di) serial data input pin. 3 clock (ck) clock input pin. the shift register shifts data on the clock's rising edge. 4 load (ld) load signal input pin. the data in the d 8 to d 15 are read on the rising edge and the current load register the is selected from among the duty register, the decode & digit register, or data registers 0 to 3. the d 0 to d 7 bits of the 16 bit shift register contain data corresponding to the same registers just described, which are read on the load signal's falling edge. 5~12 out a to out dp segment drive output pins. the a to dp outputs correspond to the seven segments. these pins output constant sink current. connect each of these pins to the corresponding led's cathode. 13, 21 p gnd ground pins, there are two which can be used to ground the output out a to out dp pins. 14 test in2 product test pin. in normal use, be sure to connect to ground. 15 test in1 product test pin. in normal use, be sure to connect to ground. 16, 17, 19, 20 dig 0 to dig 3 digit output pins. each of these pins can control one of the four seven segment digits in a display. these pins output the v cc pin voltage as a source current output. connect these pins to the led anodes. 18 v cc power pin for digit output. 22 r ext current setting pin for the out a to out dp pins. connect a resistor between this pin and ground when setting the current. 23 data out (do) serial data output pin. use when tb62709n or tb62709f devices are used in cascade connections. 24 l gnd ground pin for logic and analog circuits.
tb62709ng/fg 2005-10-06 4 timing diagram data input z transfer data to the data ? in pin on every 16 ? bit combining address (8bits) and data (8bits). after the 16 th clock signal input following this data transfer input a load signal from the ld pin. z input the load signal using an active high pulse. the register address is set on the rising edge of the load pulse. on the subsequent falling edge, the data are read as data of the mode of the register.
tb62709ng/fg 2005-10-06 5 description of operation z data input (serial in, clock, load) the data are input serially using the serial ? in pin. the data input interface consists of a total of three inputs : serial ? in, load, and clock. binary code stored in the 16 ? bit shift register offers control modes including duty control register set, digitset, decode set, and standby set, the data are shifted on the rising edge of the clock, starting from the msb. cascade ? connecting tb62709ng or TB62709FG devices provides capability for controlling a larger number of digits. the serial data in the 16 ? bit shift register are used as follows : the four bits d 15 (msb) to d 12 select the ic operating mode (table 1), while d11 to d 8 select the register corresponding to the operating mode (table 2). bits d 7 to d 0 (lsb) of the 16 ? bit shift register are used for detail settings, such as number of digits in use, character settings in each digit, and light intensity. the internal registers are loaded on the rising edge of the load signal, which causes loading of data from an external source into the d 15 (msb) to d8 bits of the shift register, operating mode and the corresponding register selection data. on the subsequent falling edge, the detail setting data of d 7 to d0 (lsb) are loaded. normally load is low. after a serial transfer of 16bits, the input of a high ? level pulse loads the data. note the following caution : use the d 15 to d 8 setting and the d 7 to d 0 detail data setting as a pair. if only the d 7 to d 0 data are input without setting d 15 to d 8 an error condition may result, in which the device will not operate normally. if the current mode is set again by a new signal, the data for d 15 to d 8 must also be re ? input. z operating precautions at power ? on or after operation in clear mode (in initial state), set the ic to normal mode again. otherwise, the ic will not drive the led. operating the ic in blank mode (all lights off) or in all on mode (all lights lit) does not affect the internal data. setting the ic to normal mode again continues the led lighting in the state governed by the settings made immediately before mode change. normal mode (not shut down, clear, blank, or all on mode) continues the operations set in load register mode. in normal mode, operations are governed by any new settings made in the load register, as soon as the changed setting values are loaded.
tb62709ng/fg 2005-10-06 6 z operating modes (table 1.) these ics support the following five operating modes : 1. blank : forcibly turns off the constant ? current output both for data and for digit setting. this mode is not affected by the values in bits d 11 to d 0 . 2. normal operate : used for display operations after the settings of the digits are complete. note that setting this mode without making any other settings will cause display of the numeral 0. 3. load register : used for the detail settings of the duty control register, for setting decode / no decode, for inputting display data, and for setting the number of digits to drive. d 11 to d 0 of the shift register are used for the detail settings of the digits currently being driven (table 2). 4. all on : forcibly turns on the data ? side constant ? current output. this mode is not affected by d 11 to d 0 . the initial setting is four digits. when the digits must be changed, use load register mode to set the number of digits to drive. 5. standby : used to set standby state (in which internal data are not cleared) and to clear data (initialization). the settings in d 3 to d 0 of the shift register determine the choice between standby state or initialization. table 1 operating mode settings register data d 15 d 14 d 13 d 12 d 11 ~d 8 d 7 ~d 4 d 3 ~d 0 hex code initial setting blank (out n & dig 0~3 all off) 0 0 0 0 ? ? ? 0 h v normal (operation) 0 0 0 1 ? ? ? 1 h load register (duty, decode, digit & data) 0 0 1 0 x x x 2xxxh all on (outn all on) 0 0 1 1 ? ? ? 3 h stand by 0 1 0 0 ? ? x 4 xh x = input h or l. " " = are not affected by the truth table.
tb62709ng/fg 2005-10-06 7 z load register selection modes (table 2) these modes select the register to provide the data to control the ic operation. the load register selection mode is determined by the settings of d 15 to d 12 and d 11 to d 8 of the shift register. 1. duty register : the data in d 7 to d 0 of this register set the digit output duty cycle. duty settings can be made in 16 steps from 0 / 16 to 15 / 16. (see table 3) 2. decode & digit register : sets decode / no decode and the number of digits to drive. decode can be set using d 7 to d 4 . the number of digits driven can be set using d 3 to d 0 . decode / no decode and the number of digits driven are set simultaneously. 3. data registers 0 to 3 : set the display data corresponding to dig0 to dig3 respectively. d 7 to d 0 of the shift register are used to set the display data. table 2 load register selection register data d 15 ~d 12 d 11 d 10 d 9 d 8 d 7 ~d 4 d 3 ~d 0 hex code load duty register 2h 0 0 0 0 x x 20xxh load decode & digit register 2h 0 0 0 1 x x 21xxh load data register 0 2h 0 0 1 0 x x 22xxh load data register 1 2h 0 0 1 1 x x 23xxh load data register 2 2h 0 1 0 0 x x 24xxh load data register 3 2h 0 1 0 1 x x 25xxh x = input h or l.
tb62709ng/fg 2005-10-06 8 duty control register settings z duty control register detail settings and operation (table 3) writing 20h to d 15 ~d 8 and writing 0~fh to d 3 ~d 0 sets the duty cycle shown in the following table for the digit ? side source driver output. the duty cycle can be set in 16 steps. the initial setting is 15 / 16. after data clear, the setting is also 15 / 16. the current settings continue until changed (by reset execution, or to the initial state, data clear state, or standby state). table 3 duty control register settings register data duty cycle d 15 ~d 8 d 7 ~d 4 d 3 d 2 d 1 d 0 hex code initial setting 0 / 16 20h ? 0 0 0 0 20x0h 1 / 16 20h ? 0 0 0 1 20x1h 2 / 16 20h ? 0 0 1 0 20x2h 3 / 16 20h ? 0 0 1 1 20x3h 4 / 16 20h ? 0 1 0 0 20x4h 5 / 16 20h ? 0 1 0 1 20x5h 6 / 16 20h ? 0 1 1 0 20x6h 7 / 16 20h ? 0 1 1 1 20x7h 8 / 16 20h ? 1 0 0 0 20x8h 9 / 16 20h ? 1 0 0 1 20x9h 10 / 16 20h ? 1 0 1 0 20xah 11 / 16 20h ? 1 0 1 1 20xbh 12 / 16 20h ? 1 1 0 0 20xch 13 / 16 20h ? 1 1 0 1 20xdh 14 / 16 20h ? 1 1 1 0 20xeh 15 / 16 20h ? 1 1 1 1 20xfh v x = input h or l. " " = are not affected by the truth table.
tb62709ng/fg 2005-10-06 9 digit settings z setting the number of digits (table 4) writing 21h to d 15 ~d 8 and at the same step writing 0h~3h to d 3 ~d 0 sets the number of digits to a maximum of four the display. the initial setting is four digits, and four will also be set by a data clear. the current settings continue until changed (by reset execution, or to the initial state, data clear state, or standby state). when changing the number of digits, also set d 7 to d 4 . table 4 digit settings register data d 15 ~d 8 d 7 ~d 4 d 3 d 2 d 1 d 0 hex code initial setting activated dig 0 only 21h x 0 0 0 0 21x0h activated dig 0~1 21h x 0 0 0 1 21x1h activated dig 0~2 21h x 0 0 1 0 21x2h activated dig 0~3 21h x 0 0 1 1 21x3h v x = input h or l. decode settings z decode settings (table 5) the settings for decode are the same as the settings for the number of digits, described under setting, above. writing 21h to d 15 ~d 8 and writing 0~1h to d 7 ~d 4 set decode mode. when using this ic for controlling the lighting on individual leds used for a dot matrix rather than a 7 ? segment display, set to no decode. as table 6 shows, d 0 in the data register is used to turn out ? a on and off ; d 1 turns out ? b on and off. the initial setting is decode mode, and decode mode will also be set by a data clear. the current settings continue until changed (by reset execution, or to the initial state, data clear state, or standby state). since d 3 to d 0 are also used for setting the number of digits, when changing the decode setting, also set d 3 to d 0 . table 5 decode settings register data d 15 ~d 8 d 7 d 6 d 5 d 4 d 3 ~d 0 hex code initial setting pass decoder (no decode) 21h 0 0 0 0 x 210xh decode 21h 0 0 0 1 x 211xh v x = input h or l.
tb62709ng/fg 2005-10-06 10 the following table shows the correspondence between the serial data and the output pins when no decode is set table 6 correspondence between serial data and output pins in no decode mode register data output initial state note d 0 out a l d 1 out b l d 2 out c l d 3 out d l d 4 out e l d 5 out f l d 6 out g l d 7 out dp l output is on when data = h and off when data = l. standby settings z standby mode settings and operation (table 7) writing 4h to d 15 ~d 12 and writing 0h to d 3 ~d 0 sets standby mode. writing 4h to d 15 ~d 12 and writing 1h to d 3 ~d 0 sets all data clear mode. standby mode maintains the settings made immediately before this mode came in force, turns the output current off, and controls the bias current flowing in the internal circuits. all data clear resets all settings to their initial states. table 7 standby settings register data d 15 ~d 8 d 7 ~d 4 d 3 d 2 d 1 d 0 hex code standby (no data clear) 4 h ? 0 0 0 0 4xx0h all data clear 4 h ? 0 0 0 1 4xx1h x = input h or l. " " are not affected by the truth table.
tb62709ng/fg 2005-10-06 11 list of character generator decoding data z character generator decoding (table 8) as the following table shows, the characters are decoded using combinations of the data in d 0 to d 3 and d 5 to d 4 . in decoding, d 6 is used exclusively for setting decimal points. spaces where (d 0 , d 1 , d 2 , d 3 ) = (0000) and (d 5 , d 4 ) = (01) are regarded as blank. table 8 list of character generator decoding data d 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 d 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 d 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 d 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 d 5 d 4 hex 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 0 0 0 1 1 d 7 d 6 x 0 dp off x 1 dp on
tb62709ng/fg 2005-10-06 12 data input (example 1: displays and blinks characters a, b, c and d in digits 0, 1, 2 and 3 respectively. period after "d" part of it, or a sentence ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? ? ? ? ?? ? ? ?? ? ? ? ??? ?
tb62709ng/fg 2005-10-06 13 state transition diagram
tb62709ng/fg 2005-10-06 14 maximum ratings (ta = 25c) characteristic symbol rating unit supply voltage for logic circuits v dd 7.0 v supply voltage v cc 17 v dig 0 to dig 3 output current i dig 400 ma out a to dp output current i out 50 ma output current for logic block i oh / i ol 5 ma input voltage v in 0.3~vdd + 0.3 v operating frequency f ck 15.0 mhz total supply current i vdd 400 ma tb62709ng 1.78 power dissipation TB62709FG p d 0.62 w operating temperature t opr 40~85 c storage temperature t stg 55~150 c electrical characteristics (unless otherwise stated, v dd = 5.0 v, v cc = 5.0 v, r ext = 760 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
tb62709ng/fg 2005-10-06 15 logic block characteristic symbol test cir cuit test condition min typ. max unit i dd1 6 standby mode, ta = 25c ? ? 200 a static power supply current for logic circuits i dd2 6 blank mode, ta = 25c ? ? 12.5 ma operating power supply current for logic circuits i dd3 6 normal ope. mode, f clk = 10mhz, data in : out a~dp = on, ta = 25c ? ? 20.5 ma high input current for logic circuits i ih ? data in, load & clock : v in = 5 v ? ? 1 a low input current for logic circuits i il ? data in, load & clock : v in = 0 v ? ? 1 a v oh1 6 data out, i oh = 1.0 ma 4.6 ? ? high output voltage for logic circuits v oh2 6 data out, i oh = 1.0 a ? v dd ? v v ol1 6 data out, i ol = 1.0 ma ? ? 0.4 low output voltage for logic circuits v ol2 6 data out, i oh = 1.0 a ? 0.1 ? v clock frequency f clk 6 cascade connected, ta = 40~85c 10 ? ? mhz
tb62709ng/fg 2005-10-06 16 switching characteristics (unless otherwise stated, v dd = 5.0 v, v cc = 5.0 v, ta = 25c) characteristic symbol test cir cuit test condition min typ. max unit data hold time (d in clock) t dho ? ? ? 10 ? ns data setup time (d in clock) t dst ? ? ? 20 ? ns t phl so c l = 10 pf ? 25 ? serial output delay time (clock d out) t plh so ? c l = 10 pf ? 25 ? ns high clock pulse width t ckh ? ? ? 30 ? ns low clock pulse width t ckl ? ? ? 30 ? ns load pulse width t wld ? ? ? 100 ? ns load clock time (clock load) t clk ld ? ? ? 50 ? ns clock load time (load clock) t ld clk ? ? ? 50 ? ns t phl seg c l = 10 pf ? ? 5.0 out a to dp output delay time (load outn) t plh seg ? c l = 10 pf ? ? 5.0 s out a to dp output rise time (outn) t r seg ? c l = 10 pf 0.2 1.0 ? s out a to dp output fall time (outn) t f seg ? c l = 10 pf 0.2 1.0 ? s t phl dig c l = 10 pf ? ? 10.0 dig 0~dig 3 output delay time (load dign) t plh dig ? c l = 10 pf ? ? 10.0 s dig 0~dig 3 output rise time (dign) t r dig ? c l = 10 pf 0.4 2.0 ? s dig 0~dig 3 output fall time (dign) t f dig c l = 10 pf 0.4 2.0 ? s
tb62709ng/fg 2005-10-06 17 recommended operating conditions (unless otherwise stated, v dd = 5.0 v, v cc = 5.0 v, ta = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
tb62709ng/fg 2005-10-06 18 test circuits (1) i cc1 , i cc2 (2) f osc tb62709ng / fg tb62709ng / fg
tb62709ng/fg 2005-10-06 19 (3) i seg (4) i leak1 , i leak2 tb62709ng / fg tb62709ng / fg
tb62709ng/fg 2005-10-06 20 (5) v out (6) i dd1 , i dd2 , i dd3 , v oh1 , v oh2 , v ol1 , v ol2 , f clk tb62709ng / fg tb62709ng / fg
tb62709ng/fg 2005-10-06 21 duty cycle settings and output current values iout-duty cycle ( tb62709ng ) iout-duty cycle ( TB62709FG ) iout-duty cycle ( tb62709ng ) iout-duty cycle ( TB62709FG )
tb62709ng/fg 2005-10-06 22 external resistance and output current values the following diagram shows application circuits. because operation may be unstable due to influences such as the electromagnetic induction of the wiring, the ic should be located as close as possible to the led. the l ? gnd and p ? gnd of the ic are connected to the substrate in the ic. take care to avoid a potential difference exceeding 0.4v at two pins. when executing the pattern layout, toshiba recommends not including inductance components in the gnd or output pin lines, and not inserting capacitance components exceeding 50pf between the r ext and gnd.
tb62709ng/fg 2005-10-06 23 application circuit example (connection example) precautions for using utmost care is necessary in the design of the output line, v cc (v dd ) and (l ? gnd, p ? gnd) line since ic may be destroyed due to short ? circuit between outputs, air contamination fault, or fault by improper grounding. tb62709ng TB62709FG
tb62709ng/fg 2005-10-06 24 package dimensions weight: 1.62 g (typ.)
tb62709ng/fg 2005-10-06 25 package dimensions weight: 0.32 g (typ.)
tb62709ng/fg 2005-10-06 26

▲Up To Search▲

Price & Availability of TB62709FG

	To Download TB62709FG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .